Dr. Fatimah Arofiati Noor S.Si, M.Si., Ibnu Syuhada, Prof. Toto Winata Ph.D., Feng Yu, Muhammad Fahlesa Fatahilah, Hutomo Suryo Wasisto, & Prof.Dr.Eng. Khairurrijal M.Si.
In this report, we study nonlinear electrical behaviors found in vertical-architecture transistors based on wrap-around-gated gallium nitride (GaN) nanowires (NWs) by extending a one-dimensional case of the Landauer-Büttiker formula. Here, the GaN NWs are considered “almost” one-dimensional ideal wires connecting the drain and source terminals, with the gate terminal serving to control the flowing current. Unlike previous models, which require several parameters and complex calculations, our proposed model only needs three parameters and simple calculations to match the experimental data. With this model, we confirm that the maximum current before saturation is a consequence of quasi-ballistic drain current. Thus, electron mobility has no effect in this device. Using a simple formulation, we discuss gating hysteresis in the device that is mediated by the selected oxide layer interface. We show that the memory effect of the device is attributed to time-delay current. The shorter gate length increases the transmission coefficient. As a result, the model can be employed to predict the next-generation NW transistor performance.